Avera Semi, a GLOBALFOUNDRIES subsidiary, uses a broad range of Cadence custom IC, digital, system and verification, and PCB design and analysis EDA solutions
Cadence Design Systems, Inc. announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has come to rely on the features, capacity, speed and scalability of the Cadence® digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows. Establishing Cadence as their primary vendor has enabled them to improve engineering productivity.
Avera Semi has successfully completed several large, complex 12nm and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus™ Implementation System, the Genus™Synthesis Solution, the Tempus™ Timing Signoff Solution and Xcelium Parallel Logic Simulation as well as the Virtuoso custom IC design platform, Spectre® circuit simulation platform and Allegro and Sigrity™tools, which are part of following product categories:
- Digital and Signoff: The parallelized, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
- System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
- Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
- PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tools’ customizability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.
Read More: SalesTech Interview With Chris Harrington, Chief Operating Officer At InsideSales.Com
“Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow,” said Kevin O’Buckley, GM at Avera Semi. “We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. Standardizing on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centers, wired communications, and machine learning and artificial intelligence applications.”
Read More: Invoca Named Leader In G2 Crowd Enterprise Grid For Call Tracking, Receiving Top Overall Score
“Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We are always working to optimize design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”
Read More: ZeroBounce Upgrades Data Center Infrastructure To Boost Email Verification API Speed
